The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. As the semiconductor industry has progressed into nanometer technology process nodes in pursuit of higher device density, higher performance, and lower costs, challenges from both fabrication and design issues have resulted in the development of three-dimensional designs, such as the fin field effect transistor (FinFET). FinFETs are fabricated with a thin vertical “fin” (or fin structure) extending from a substrate. The channel of the FinFET is formed in this vertical fin. A gate is provided over three sides (e.g., wrapping) the fin. Advantages of the FinFET may include reducing the short channel effect and increasing the current flow.
Although existing FinFET manufacturing processes have been generally adequate for their intended purposes, as the size of FinFET scaling-down continues, they have not been entirely satisfactory in formation of isolation structure for adjacent fins in the FinFET device structure.